As the Internet of Things (IoT) is increasingly integrated into our everyday life, the demand for different sensor modalities, especially imaging, is rising. IoT imagers are often compact and have small form-factor batteries and thus must be designed with both low power (improving battery life) and high image quality (maximizing utility). Previously reported sensors adopted motion-detection (MD) triggering of full-array capture where motion detection is performed on a heavily subsampled frame to enable continuous low-power operation. Motion detection limits energy-hungry full-array captures to cases where activity is detected. To further reduce power consumption, the full-frame capture energy itself needs to be addressed, which is typically dominated by the ADC.
Conventional imagers use a single slope ADC with 4T pixel structure, which provides high fidelity but is inherently energy inefficient. This is particularly the case at higher resolution due to its exponential energy scaling with bit width or when used in conjunction with sub-sampling. SAR-based ADCs have superior energy efficiency and are used extensively in other application areas. However, to date SAR ADCs have been rarely used in imagers due to their large size and limited accuracy. To achieve both high quality and low power, this disclosure proposes an energy-efficient, low-noise capacitor array-assisted charge-injection SAR ADC (c-ciSAR) structure. The structure merges an area efficient charge-injection cell (ci-cell) with a small capacitor array structure to extend its performance to 10b. The merged capacitor array and charge-injection cell structure achieves significantly higher ADC energy efficiency compared to a single-slope ADC, with a measured ADC FoM of 14.4 uV·nJ (full capture mode) and 90.4 uV·pJ (motion detection mode).
This section provides background information related to the present disclosure which is not necessarily prior art.